as: i386-Options
9.15.1 Options
--------------
The i386 version of 'as' has a few machine dependent options:
'--32 | --x32 | --64'
Select the word size, either 32 bits or 64 bits. '--32' implies
Intel i386 architecture, while '--x32' and '--64' imply AMD x86-64
architecture with 32-bit or 64-bit word-size respectively.
These options are only available with the ELF object file format,
and require that the necessary BFD support has been included (on a
32-bit platform you have to add -enable-64-bit-bfd to configure
enable 64-bit usage and use x86-64 as target platform).
'-n'
By default, x86 GAS replaces multiple nop instructions used for
alignment within code sections with multi-byte nop instructions
such as leal 0(%esi,1),%esi. This switch disables the optimization
if a single byte nop (0x90) is explicitly specified as the fill
byte for alignment.
'--divide'
On SVR4-derived platforms, the character '/' is treated as a
comment character, which means that it cannot be used in
expressions. The '--divide' option turns '/' into a normal
character. This does not disable '/' at the beginning of a line
starting a comment, or affect using '#' for starting a comment.
'-march=CPU[+EXTENSION...]'
This option specifies the target processor. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target processor. The
following processor names are recognized: 'i8086', 'i186', 'i286',
'i386', 'i486', 'i586', 'i686', 'pentium', 'pentiumpro',
'pentiumii', 'pentiumiii', 'pentium4', 'prescott', 'nocona',
'core', 'core2', 'corei7', 'l1om', 'k1om', 'iamcu', 'k6', 'k6_2',
'athlon', 'opteron', 'k8', 'amdfam10', 'bdver1', 'bdver2',
'bdver3', 'bdver4', 'znver1', 'znver2', 'btver1', 'btver2',
'generic32' and 'generic64'.
In addition to the basic instruction set, the assembler can be told
to accept various extension mnemonics. For example,
'-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The
following extensions are currently supported: '8087', '287', '387',
'687', 'no87', 'no287', 'no387', 'no687', 'cmov', 'nocmov', 'fxsr',
'nofxsr', 'mmx', 'nommx', 'sse', 'sse2', 'sse3', 'ssse3', 'sse4.1',
'sse4.2', 'sse4', 'nosse', 'nosse2', 'nosse3', 'nossse3',
'nosse4.1', 'nosse4.2', 'nosse4', 'avx', 'avx2', 'noavx', 'noavx2',
'adx', 'rdseed', 'prfchw', 'smap', 'mpx', 'sha', 'rdpid',
'ptwrite', 'cet', 'gfni', 'vaes', 'vpclmulqdq', 'prefetchwt1',
'clflushopt', 'se1', 'clwb', 'movdiri', 'movdir64b', 'avx512f',
'avx512cd', 'avx512er', 'avx512pf', 'avx512vl', 'avx512bw',
'avx512dq', 'avx512ifma', 'avx512vbmi', 'avx512_4fmaps',
'avx512_4vnniw', 'avx512_vpopcntdq', 'avx512_vbmi2', 'avx512_vnni',
'avx512_bitalg', 'noavx512f', 'noavx512cd', 'noavx512er',
'noavx512pf', 'noavx512vl', 'noavx512bw', 'noavx512dq',
'noavx512ifma', 'noavx512vbmi', 'noavx512_4fmaps',
'noavx512_4vnniw', 'noavx512_vpopcntdq', 'noavx512_vbmi2',
'noavx512_vnni', 'noavx512_bitalg', 'vmx', 'vmfunc', 'smx',
'xsave', 'xsaveopt', 'xsavec', 'xsaves', 'aes', 'pclmul',
'fsgsbase', 'rdrnd', 'f16c', 'bmi2', 'fma', 'movbe', 'ept',
'lzcnt', 'hle', 'rtm', 'invpcid', 'clflush', 'mwaitx', 'clzero',
'wbnoinvd', 'pconfig', 'waitpkg', 'cldemote', 'lwp', 'fma4', 'xop',
'cx16', 'syscall', 'rdtscp', '3dnow', '3dnowa', 'sse4a', 'sse5',
'svme', 'abm' and 'padlock'. Note that rather than extending a
basic instruction set, the extension mnemonics starting with 'no'
revoke the respective functionality.
When the '.arch' directive is used with '-march', the '.arch'
directive will take precedent.
'-mtune=CPU'
This option specifies a processor to optimize for. When used in
conjunction with the '-march' option, only instructions of the
processor specified by the '-march' option will be generated.
Valid CPU values are identical to the processor list of
'-march=CPU'.
'-msse2avx'
This option specifies that the assembler should encode SSE
instructions with VEX prefix.
'-msse-check=NONE'
'-msse-check=WARNING'
'-msse-check=ERROR'
These options control if the assembler should check SSE
instructions. '-msse-check=NONE' will make the assembler not to
check SSE instructions, which is the default.
'-msse-check=WARNING' will make the assembler issue a warning for
any SSE instruction. '-msse-check=ERROR' will make the assembler
issue an error for any SSE instruction.
'-mavxscalar=128'
'-mavxscalar=256'
These options control how the assembler should encode scalar AVX
instructions. '-mavxscalar=128' will encode scalar AVX
instructions with 128bit vector length, which is the default.
'-mavxscalar=256' will encode scalar AVX instructions with 256bit
vector length.
'-mvexwig=0'
'-mvexwig=1'
These options control how the assembler should encode VEX.W-ignored
(WIG) VEX instructions. '-mvexwig=0' will encode WIG VEX
instructions with vex.w = 0, which is the default. '-mvexwig=1'
will encode WIG EVEX instructions with vex.w = 1.
'-mevexlig=128'
'-mevexlig=256'
'-mevexlig=512'
These options control how the assembler should encode
length-ignored (LIG) EVEX instructions. '-mevexlig=128' will
encode LIG EVEX instructions with 128bit vector length, which is
the default. '-mevexlig=256' and '-mevexlig=512' will encode LIG
EVEX instructions with 256bit and 512bit vector length,
respectively.
'-mevexwig=0'
'-mevexwig=1'
These options control how the assembler should encode w-ignored
(WIG) EVEX instructions. '-mevexwig=0' will encode WIG EVEX
instructions with evex.w = 0, which is the default. '-mevexwig=1'
will encode WIG EVEX instructions with evex.w = 1.
'-mmnemonic=ATT'
'-mmnemonic=INTEL'
This option specifies instruction mnemonic for matching
instructions. The '.att_mnemonic' and '.intel_mnemonic' directives
will take precedent.
'-msyntax=ATT'
'-msyntax=INTEL'
This option specifies instruction syntax when processing
instructions. The '.att_syntax' and '.intel_syntax' directives
will take precedent.
'-mnaked-reg'
This option specifies that registers don't require a '%' prefix.
The '.att_syntax' and '.intel_syntax' directives will take
precedent.
'-madd-bnd-prefix'
This option forces the assembler to add BND prefix to all branches,
even if such prefix was not explicitly specified in the source
code.
'-mno-shared'
On ELF target, the assembler normally optimizes out non-PLT
relocations against defined non-weak global branch targets with
default visibility. The '-mshared' option tells the assembler to
generate code which may go into a shared library where all non-weak
global branch targets with default visibility can be preempted.
The resulting code is slightly bigger. This option only affects
the handling of branch instructions.
'-mbig-obj'
On x86-64 PE/COFF target this option forces the use of big object
file format, which allows more than 32768 sections.
'-momit-lock-prefix=NO'
'-momit-lock-prefix=YES'
These options control how the assembler should encode lock prefix.
This option is intended as a workaround for processors, that fail
on lock prefix. This option can only be safely used with
single-core, single-thread computers '-momit-lock-prefix=YES' will
omit all lock prefixes. '-momit-lock-prefix=NO' will encode lock
prefix as usual, which is the default.
'-mfence-as-lock-add=NO'
'-mfence-as-lock-add=YES'
These options control how the assembler should encode lfence,
mfence and sfence. '-mfence-as-lock-add=YES' will encode lfence,
mfence and sfence as 'lock addl $0x0, (%rsp)' in 64-bit mode and
'lock addl $0x0, (%esp)' in 32-bit mode. '-mfence-as-lock-add=NO'
will encode lfence, mfence and sfence as usual, which is the
default.
'-mrelax-relocations=NO'
'-mrelax-relocations=YES'
These options control whether the assembler should generate relax
relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX
and R_X86_64_REX_GOTPCRELX, in 64-bit mode.
'-mrelax-relocations=YES' will generate relax relocations.
'-mrelax-relocations=NO' will not generate relax relocations. The
default can be controlled by a configure option
'--enable-x86-relax-relocations'.
'-mx86-used-note=NO'
'-mx86-used-note=YES'
These options control whether the assembler should generate
GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED GNU
property notes. The default can be controlled by the
'--enable-x86-used-note' configure option.
'-mevexrcig=RNE'
'-mevexrcig=RD'
'-mevexrcig=RU'
'-mevexrcig=RZ'
These options control how the assembler should encode SAE-only EVEX
instructions. '-mevexrcig=RNE' will encode RC bits of EVEX
instruction with 00, which is the default. '-mevexrcig=RD',
'-mevexrcig=RU' and '-mevexrcig=RZ' will encode SAE-only EVEX
instructions with 01, 10 and 11 RC bits, respectively.
'-mamd64'
'-mintel64'
This option specifies that the assembler should accept only AMD64
or Intel64 ISA in 64-bit mode. The default is to accept both.
'-O0 | -O | -O1 | -O2 | -Os'
Optimize instruction encoding with smaller instruction size. '-O'
and '-O1' encode 64-bit register load instructions with 64-bit
immediate as 32-bit register load instructions with 31-bit or
32-bits immediates and encode 64-bit register clearing instructions
with 32-bit register clearing instructions. '-O2' includes '-O1'
optimization plus encodes 256-bit and 512-bit vector register
clearing instructions with 128-bit vector register clearing
instructions. '-Os' includes '-O2' optimization plus encodes
16-bit, 32-bit and 64-bit register tests with immediate as 8-bit
register test with immediate. '-O0' turns off this optimization.
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