as: SH Floating Point
9.42.3 Floating Point
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SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other
SH groups can use '.float' directive to generate IEEE floating-point
numbers.
SH2E and SH3E support single-precision floating point calculations as
well as entirely PCAPI compatible emulation of double-precision floating
point calculations. SH2E and SH3E instructions are a subset of the
floating point calculations conforming to the IEEE754 standard.
In addition to single-precision and double-precision floating-point
operation capability, the on-chip FPU of SH4 has a 128-bit graphic
engine that enables 32-bit floating-point data to be processed 128 bits
at a time. It also supports 4 * 4 array operations and inner product
operations. Also, a superscalar architecture is employed that enables
simultaneous execution of two instructions (including FPU instructions),
providing performance of up to twice that of conventional architectures
at the same frequency.
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