as: MIPS Options
9.26.1 Assembler options
------------------------
The MIPS configurations of GNU 'as' support these special options:
'-G NUM'
Set the "small data" limit to N bytes. The default limit is 8
bytes. 
Controlling the use of small data accesses MIPS
Small Data.
'-EB'
'-EL'
Any MIPS configuration of 'as' can select big-endian or
little-endian output at run time (unlike the other GNU development
tools, which must be configured for one or the other). Use '-EB'
to select big-endian output, and '-EL' for little-endian.
'-KPIC'
Generate SVR4-style PIC. This option tells the assembler to
generate SVR4-style position-independent macro expansions. It also
tells the assembler to mark the output file as PIC.
'-mvxworks-pic'
Generate VxWorks PIC. This option tells the assembler to generate
VxWorks-style position-independent macro expansions.
'-mips1'
'-mips2'
'-mips3'
'-mips4'
'-mips5'
'-mips32'
'-mips32r2'
'-mips32r3'
'-mips32r5'
'-mips32r6'
'-mips64'
'-mips64r2'
'-mips64r3'
'-mips64r5'
'-mips64r6'
Generate code for a particular MIPS Instruction Set Architecture
level. '-mips1' corresponds to the R2000 and R3000 processors,
'-mips2' to the R6000 processor, '-mips3' to the R4000 processor,
and '-mips4' to the R8000 and R10000 processors. '-mips5',
'-mips32', '-mips32r2', '-mips32r3', '-mips32r5', '-mips32r6',
'-mips64', '-mips64r2', '-mips64r3', '-mips64r5', and '-mips64r6'
correspond to generic MIPS V, MIPS32, MIPS32 Release 2, MIPS32
Release 3, MIPS32 Release 5, MIPS32 Release 6, MIPS64, and MIPS64
Release 2, MIPS64 Release 3, MIPS64 Release 5, and MIPS64 Release 6
ISA processors, respectively. You can also switch instruction sets
during the assembly; see Directives to override the ISA
level MIPS ISA.
'-mgp32'
'-mfp32'
Some macros have different expansions for 32-bit and 64-bit
registers. The register sizes are normally inferred from the ISA
and ABI, but these flags force a certain group of registers to be
treated as 32 bits wide at all times. '-mgp32' controls the size
of general-purpose registers and '-mfp32' controls the size of
floating-point registers.
The '.set gp=32' and '.set fp=32' directives allow the size of
registers to be changed for parts of an object. The default value
is restored by '.set gp=default' and '.set fp=default'.
On some MIPS variants there is a 32-bit mode flag; when this flag
is set, 64-bit instructions generate a trap. Also, some 32-bit
OSes only save the 32-bit registers on a context switch, so it is
essential never to use the 64-bit registers.
'-mgp64'
'-mfp64'
Assume that 64-bit registers are available. This is provided in
the interests of symmetry with '-mgp32' and '-mfp32'.
The '.set gp=64' and '.set fp=64' directives allow the size of
registers to be changed for parts of an object. The default value
is restored by '.set gp=default' and '.set fp=default'.
'-mfpxx'
Make no assumptions about whether 32-bit or 64-bit floating-point
registers are available. This is provided to support having
modules compatible with either '-mfp32' or '-mfp64'. This option
can only be used with MIPS II and above.
The '.set fp=xx' directive allows a part of an object to be marked
as not making assumptions about 32-bit or 64-bit FP registers. The
default value is restored by '.set fp=default'.
'-modd-spreg'
'-mno-odd-spreg'
Enable use of floating-point operations on odd-numbered
single-precision registers when supported by the ISA. '-mfpxx'
implies '-mno-odd-spreg', otherwise the default is '-modd-spreg'
'-mips16'
'-no-mips16'
Generate code for the MIPS 16 processor. This is equivalent to
putting '.module mips16' at the start of the assembly file.
'-no-mips16' turns off this option.
'-mmips16e2'
'-mno-mips16e2'
Enable the use of MIPS16e2 instructions in MIPS16 mode. This is
equivalent to putting '.module mips16e2' at the start of the
assembly file. '-mno-mips16e2' turns off this option.
'-mmicromips'
'-mno-micromips'
Generate code for the microMIPS processor. This is equivalent to
putting '.module micromips' at the start of the assembly file.
'-mno-micromips' turns off this option. This is equivalent to
putting '.module nomicromips' at the start of the assembly file.
'-msmartmips'
'-mno-smartmips'
Enables the SmartMIPS extensions to the MIPS32 instruction set,
which provides a number of new instructions which target smartcard
and cryptographic applications. This is equivalent to putting
'.module smartmips' at the start of the assembly file.
'-mno-smartmips' turns off this option.
'-mips3d'
'-no-mips3d'
Generate code for the MIPS-3D Application Specific Extension. This
tells the assembler to accept MIPS-3D instructions. '-no-mips3d'
turns off this option.
'-mdmx'
'-no-mdmx'
Generate code for the MDMX Application Specific Extension. This
tells the assembler to accept MDMX instructions. '-no-mdmx' turns
off this option.
'-mdsp'
'-mno-dsp'
Generate code for the DSP Release 1 Application Specific Extension.
This tells the assembler to accept DSP Release 1 instructions.
'-mno-dsp' turns off this option.
'-mdspr2'
'-mno-dspr2'
Generate code for the DSP Release 2 Application Specific Extension.
This option implies '-mdsp'. This tells the assembler to accept
DSP Release 2 instructions. '-mno-dspr2' turns off this option.
'-mdspr3'
'-mno-dspr3'
Generate code for the DSP Release 3 Application Specific Extension.
This option implies '-mdsp' and '-mdspr2'. This tells the
assembler to accept DSP Release 3 instructions. '-mno-dspr3' turns
off this option.
'-mmt'
'-mno-mt'
Generate code for the MT Application Specific Extension. This
tells the assembler to accept MT instructions. '-mno-mt' turns off
this option.
'-mmcu'
'-mno-mcu'
Generate code for the MCU Application Specific Extension. This
tells the assembler to accept MCU instructions. '-mno-mcu' turns
off this option.
'-mmsa'
'-mno-msa'
Generate code for the MIPS SIMD Architecture Extension. This tells
the assembler to accept MSA instructions. '-mno-msa' turns off
this option.
'-mxpa'
'-mno-xpa'
Generate code for the MIPS eXtended Physical Address (XPA)
Extension. This tells the assembler to accept XPA instructions.
'-mno-xpa' turns off this option.
'-mvirt'
'-mno-virt'
Generate code for the Virtualization Application Specific
Extension. This tells the assembler to accept Virtualization
instructions. '-mno-virt' turns off this option.
'-mcrc'
'-mno-crc'
Generate code for the cyclic redundancy check (CRC) Application
Specific Extension. This tells the assembler to accept CRC
instructions. '-mno-crc' turns off this option.
'-mginv'
'-mno-ginv'
Generate code for the Global INValidate (GINV) Application Specific
Extension. This tells the assembler to accept GINV instructions.
'-mno-ginv' turns off this option.
'-mloongson-mmi'
'-mno-loongson-mmi'
Generate code for the Loongson MultiMedia extensions Instructions
(MMI) Application Specific Extension. This tells the assembler to
accept MMI instructions. '-mno-loongson-mmi' turns off this
option.
'-mloongson-cam'
'-mno-loongson-cam'
Generate code for the Loongson Content Address Memory (CAM)
Application Specific Extension. This tells the assembler to accept
CAM instructions. '-mno-loongson-cam' turns off this option.
'-mloongson-ext'
'-mno-loongson-ext'
Generate code for the Loongson EXTensions (EXT) instructions
Application Specific Extension. This tells the assembler to accept
EXT instructions. '-mno-loongson-ext' turns off this option.
'-mloongson-ext2'
'-mno-loongson-ext2'
Generate code for the Loongson EXTensions R2 (EXT2) instructions
Application Specific Extension. This tells the assembler to accept
EXT2 instructions. '-mno-loongson-ext2' turns off this option.
'-minsn32'
'-mno-insn32'
Only use 32-bit instruction encodings when generating code for the
microMIPS processor. This option inhibits the use of any 16-bit
instructions. This is equivalent to putting '.set insn32' at the
start of the assembly file. '-mno-insn32' turns off this option.
This is equivalent to putting '.set noinsn32' at the start of the
assembly file. By default '-mno-insn32' is selected, allowing all
instructions to be used.
'-mfix7000'
'-mno-fix7000'
Cause nops to be inserted if the read of the destination register
of an mfhi or mflo instruction occurs in the following two
instructions.
'-mfix-rm7000'
'-mno-fix-rm7000'
Cause nops to be inserted if a dmult or dmultu instruction is
followed by a load instruction.
'-mfix-loongson2f-jump'
'-mno-fix-loongson2f-jump'
Eliminate instruction fetch from outside 256M region to work around
the Loongson2F 'jump' instructions. Without it, under extreme
cases, the kernel may crash. The issue has been solved in latest
processor batches, but this fix has no side effect to them.
'-mfix-loongson2f-nop'
'-mno-fix-loongson2f-nop'
Replace nops by 'or at,at,zero' to work around the Loongson2F 'nop'
errata. Without it, under extreme cases, the CPU might deadlock.
The issue has been solved in later Loongson2F batches, but this fix
has no side effect to them.
'-mfix-vr4120'
'-mno-fix-vr4120'
Insert nops to work around certain VR4120 errata. This option is
intended to be used on GCC-generated code: it is not designed to
catch all problems in hand-written assembler code.
'-mfix-vr4130'
'-mno-fix-vr4130'
Insert nops to work around the VR4130 'mflo'/'mfhi' errata.
'-mfix-24k'
'-mno-fix-24k'
Insert nops to work around the 24K 'eret'/'deret' errata.
'-mfix-cn63xxp1'
'-mno-fix-cn63xxp1'
Replace 'pref' hints 0 - 4 and 6 - 24 with hint 28 to work around
certain CN63XXP1 errata.
'-mfix-r5900'
'-mno-fix-r5900'
Do not attempt to schedule the preceding instruction into the delay
slot of a branch instruction placed at the end of a short loop of
six instructions or fewer and always schedule a 'nop' instruction
there instead. The short loop bug under certain conditions causes
loops to execute only once or twice, due to a hardware bug in the
R5900 chip.
'-m4010'
'-no-m4010'
Generate code for the LSI R4010 chip. This tells the assembler to
accept the R4010-specific instructions ('addciu', 'ffc', etc.), and
to not schedule 'nop' instructions around accesses to the 'HI' and
'LO' registers. '-no-m4010' turns off this option.
'-m4650'
'-no-m4650'
Generate code for the MIPS R4650 chip. This tells the assembler to
accept the 'mad' and 'madu' instruction, and to not schedule 'nop'
instructions around accesses to the 'HI' and 'LO' registers.
'-no-m4650' turns off this option.
'-m3900'
'-no-m3900'
'-m4100'
'-no-m4100'
For each option '-mNNNN', generate code for the MIPS RNNNN chip.
This tells the assembler to accept instructions specific to that
chip, and to schedule for that chip's hazards.
'-march=CPU'
Generate code for a particular MIPS CPU. It is exactly equivalent
to '-mCPU', except that there are more value of CPU understood.
Valid CPU value are:
2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130,
vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231,
rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000,
10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem,
4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc,
24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1,
34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf,
74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1,
interaptiv, interaptiv-mr2, m5100, m5101, p5600, 5kc, 5kf,
20kc, 25kf, sb1, sb1a, i6400, p6600, loongson2e, loongson2f,
gs464, gs464e, gs264e, octeon, octeon+, octeon2, octeon3, xlr,
xlp
For compatibility reasons, 'Nx' and 'Bfx' are accepted as synonyms
for 'Nf1_1'. These values are deprecated.
'-mtune=CPU'
Schedule and tune for a particular MIPS CPU. Valid CPU values are
identical to '-march=CPU'.
'-mabi=ABI'
Record which ABI the source code uses. The recognized arguments
are: '32', 'n32', 'o64', '64' and 'eabi'.
'-msym32'
'-mno-sym32'
Equivalent to adding '.set sym32' or '.set nosym32' to the
beginning of the assembler input. MIPS Symbol Sizes.
'-nocpp'
This option is ignored. It is accepted for command-line
compatibility with other assemblers, which use it to turn off C
style preprocessing. With GNU 'as', there is no need for '-nocpp',
because the GNU assembler itself never runs the C preprocessor.
'-msoft-float'
'-mhard-float'
Disable or enable floating-point instructions. Note that by
default floating-point instructions are always allowed even with
CPU targets that don't have support for these instructions.
'-msingle-float'
'-mdouble-float'
Disable or enable double-precision floating-point operations. Note
that by default double-precision floating-point operations are
always allowed even with CPU targets that don't have support for
these operations.
'--construct-floats'
'--no-construct-floats'
The '--no-construct-floats' option disables the construction of
double width floating point constants by loading the two halves of
the value into the two single width floating point registers that
make up the double width register. This feature is useful if the
processor support the FR bit in its status register, and this bit
is known (by the programmer) to be set. This bit prevents the
aliasing of the double width register by the single width
registers.
By default '--construct-floats' is selected, allowing construction
of these floating point constants.
'--relax-branch'
'--no-relax-branch'
The '--relax-branch' option enables the relaxation of out-of-range
branches. Any branches whose target cannot be reached directly are
converted to a small instruction sequence including an
inverse-condition branch to the physically next instruction, and a
jump to the original target is inserted between the two
instructions. In PIC code the jump will involve further
instructions for address calculation.
The 'BC1ANY2F', 'BC1ANY2T', 'BC1ANY4F', 'BC1ANY4T', 'BPOSGE32' and
'BPOSGE64' instructions are excluded from relaxation, because they
have no complementing counterparts. They could be relaxed with the
use of a longer sequence involving another branch, however this has
not been implemented and if their target turns out of reach, they
produce an error even if branch relaxation is enabled.
Also no MIPS16 branches are ever relaxed.
By default '--no-relax-branch' is selected, causing any
out-of-range branches to produce an error.
'-mignore-branch-isa'
'-mno-ignore-branch-isa'
Ignore branch checks for invalid transitions between ISA modes.
The semantics of branches does not provide for an ISA mode switch,
so in most cases the ISA mode a branch has been encoded for has to
be the same as the ISA mode of the branch's target label. If the
ISA modes do not match, then such a branch, if taken, will cause
the ISA mode to remain unchanged and instructions that follow will
be executed in the wrong ISA mode causing the program to misbehave
or crash.
In the case of the 'BAL' instruction it may be possible to relax it
to an equivalent 'JALX' instruction so that the ISA mode is
switched at the run time as required. For other branches no
relaxation is possible and therefore GAS has checks implemented
that verify in branch assembly that the two ISA modes match, and
report an error otherwise so that the problem with code can be
diagnosed at the assembly time rather than at the run time.
However some assembly code, including generated code produced by
some versions of GCC, may incorrectly include branches to data
labels, which appear to require a mode switch but are either dead
or immediately followed by valid instructions encoded for the same
ISA the branch has been encoded for. While not strictly correct at
the source level such code will execute as intended, so to help
with these cases '-mignore-branch-isa' is supported which disables
ISA mode checks for branches.
By default '-mno-ignore-branch-isa' is selected, causing any
invalid branch requiring a transition between ISA modes to produce
an error.
'-mnan=ENCODING'
This option indicates whether the source code uses the IEEE 2008
NaN encoding ('-mnan=2008') or the original MIPS encoding
('-mnan=legacy'). It is equivalent to adding a '.nan' directive to
the beginning of the source file. MIPS NaN Encodings.
'-mnan=legacy' is the default if no '-mnan' option or '.nan'
directive is used.
'--trap'
'--no-break'
'as' automatically macro expands certain division and
multiplication instructions to check for overflow and division by
zero. This option causes 'as' to generate code to take a trap
exception rather than a break exception when an error is detected.
The trap instructions are only supported at Instruction Set
Architecture level 2 and higher.
'--break'
'--no-trap'
Generate code to take a break exception rather than a trap
exception when an error is detected. This is the default.
'-mpdr'
'-mno-pdr'
Control generation of '.pdr' sections. Off by default on IRIX, on
elsewhere.
'-mshared'
'-mno-shared'
When generating code using the Unix calling conventions (selected
by '-KPIC' or '-mcall_shared'), gas will normally generate code
which can go into a shared library. The '-mno-shared' option tells
gas to generate code which uses the calling convention, but can not
go into a shared library. The resulting code is slightly more
efficient. This option only affects the handling of the '.cpload'
and '.cpsetup' pseudo-ops.
Info Catalog
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