as: ARM Options
9.4.1 Options
-------------
'-mcpu=PROCESSOR[+EXTENSION...]'
This option specifies the target processor. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target processor. The
following processor names are recognized: 'arm1', 'arm2', 'arm250',
'arm3', 'arm6', 'arm60', 'arm600', 'arm610', 'arm620', 'arm7',
'arm7m', 'arm7d', 'arm7dm', 'arm7di', 'arm7dmi', 'arm70', 'arm700',
'arm700i', 'arm710', 'arm710t', 'arm720', 'arm720t', 'arm740t',
'arm710c', 'arm7100', 'arm7500', 'arm7500fe', 'arm7t', 'arm7tdmi',
'arm7tdmi-s', 'arm8', 'arm810', 'strongarm', 'strongarm1',
'strongarm110', 'strongarm1100', 'strongarm1110', 'arm9', 'arm920',
'arm920t', 'arm922t', 'arm940t', 'arm9tdmi', 'fa526' (Faraday FA526
processor), 'fa626' (Faraday FA626 processor), 'arm9e', 'arm926e',
'arm926ej-s', 'arm946e-r0', 'arm946e', 'arm946e-s', 'arm966e-r0',
'arm966e', 'arm966e-s', 'arm968e-s', 'arm10t', 'arm10tdmi',
'arm10e', 'arm1020', 'arm1020t', 'arm1020e', 'arm1022e',
'arm1026ej-s', 'fa606te' (Faraday FA606TE processor), 'fa616te'
(Faraday FA616TE processor), 'fa626te' (Faraday FA626TE processor),
'fmp626' (Faraday FMP626 processor), 'fa726te' (Faraday FA726TE
processor), 'arm1136j-s', 'arm1136jf-s', 'arm1156t2-s',
'arm1156t2f-s', 'arm1176jz-s', 'arm1176jzf-s', 'mpcore',
'mpcorenovfp', 'cortex-a5', 'cortex-a7', 'cortex-a8', 'cortex-a9',
'cortex-a15', 'cortex-a17', 'cortex-a32', 'cortex-a35',
'cortex-a53', 'cortex-a55', 'cortex-a57', 'cortex-a72',
'cortex-a73', 'cortex-a75', 'cortex-a76', 'ares', 'cortex-r4',
'cortex-r4f', 'cortex-r5', 'cortex-r7', 'cortex-r8', 'cortex-r52',
'cortex-m33', 'cortex-m23', 'cortex-m7', 'cortex-m4', 'cortex-m3',
'cortex-m1', 'cortex-m0', 'cortex-m0plus', 'exynos-m1',
'marvell-pj4', 'marvell-whitney', 'xgene1', 'xgene2', 'ep9312'
(ARM920 with Cirrus Maverick coprocessor), 'i80200' (Intel XScale
processor) 'iwmmxt' (Intel(r) XScale processor with Wireless
MMX(tm) technology coprocessor) and 'xscale'. The special name
'all' may be used to allow the assembler to accept instructions
valid for any ARM processor.
In addition to the basic instruction set, the assembler can be told
to accept various extension mnemonics that extend the processor
using the co-processor instruction space. For example,
'-mcpu=arm920+maverick' is equivalent to specifying '-mcpu=ep9312'.
Multiple extensions may be specified, separated by a '+'. The
extensions should be specified in ascending alphabetical order.
Some extensions may be restricted to particular architectures; this
is documented in the list of extensions below.
Extension mnemonics may also be removed from those the assembler
accepts. This is done be prepending 'no' to the option that adds
the extension. Extensions that are removed should be listed after
all extensions which have been added, again in ascending
alphabetical order. For example, '-mcpu=ep9312+nomaverick' is
equivalent to specifying '-mcpu=arm920'.
The following extensions are currently supported: 'crc' 'crypto'
(Cryptography Extensions for v8-A architecture, implies 'fp+simd'),
'dotprod' (Dot Product Extensions for v8.2-A architecture, implies
'fp+simd'), 'fp' (Floating Point Extensions for v8-A architecture),
'fp16' (FP16 Extensions for v8.2-A architecture, implies 'fp'),
'fp16fml' (FP16 Floating Point Multiplication Variant Extensions
for v8.2-A architecture, implies 'fp16'), 'idiv' (Integer Divide
Extensions for v7-A and v7-R architectures), 'iwmmxt', 'iwmmxt2',
'xscale', 'maverick', 'mp' (Multiprocessing Extensions for v7-A and
v7-R architectures), 'os' (Operating System for v6M architecture),
'predres' (Execution and Data Prediction Restriction Instruction
for v8-A architectures, added by default from v8.5-A), 'sb'
(Speculation Barrier Instruction for v8-A architectures, added by
default from v8.5-A), 'sec' (Security Extensions for v6K and v7-A
architectures), 'simd' (Advanced SIMD Extensions for v8-A
architecture, implies 'fp'), 'virt' (Virtualization Extensions for
v7-A architecture, implies 'idiv'), 'pan' (Privileged Access Never
Extensions for v8-A architecture), 'ras' (Reliability, Availability
and Serviceability extensions for v8-A architecture), 'rdma'
(ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
'simd') and 'xscale'.
'-march=ARCHITECTURE[+EXTENSION...]'
This option specifies the target architecture. The assembler will
issue an error message if an attempt is made to assemble an
instruction which will not execute on the target architecture. The
following architecture names are recognized: 'armv1', 'armv2',
'armv2a', 'armv2s', 'armv3', 'armv3m', 'armv4', 'armv4xm',
'armv4t', 'armv4txm', 'armv5', 'armv5t', 'armv5txm', 'armv5te',
'armv5texp', 'armv6', 'armv6j', 'armv6k', 'armv6z', 'armv6kz',
'armv6-m', 'armv6s-m', 'armv7', 'armv7-a', 'armv7ve', 'armv7-r',
'armv7-m', 'armv7e-m', 'armv8-a', 'armv8.1-a', 'armv8.2-a',
'armv8.3-a', 'armv8-r', 'armv8.4-a', 'armv8.5-a', 'iwmmxt'
'iwmmxt2' and 'xscale'. If both '-mcpu' and '-march' are
specified, the assembler will use the setting for '-mcpu'.
The architecture option can be extended with the same instruction
set extension options as the '-mcpu' option.
'-mfpu=FLOATING-POINT-FORMAT'
This option specifies the floating point format to assemble for.
The assembler will issue an error message if an attempt is made to
assemble an instruction which will not execute on the target
floating point unit. The following format options are recognized:
'softfpa', 'fpe', 'fpe2', 'fpe3', 'fpa', 'fpa10', 'fpa11',
'arm7500fe', 'softvfp', 'softvfp+vfp', 'vfp', 'vfp10', 'vfp10-r0',
'vfp9', 'vfpxd', 'vfpv2', 'vfpv3', 'vfpv3-fp16', 'vfpv3-d16',
'vfpv3-d16-fp16', 'vfpv3xd', 'vfpv3xd-d16', 'vfpv4', 'vfpv4-d16',
'fpv4-sp-d16', 'fpv5-sp-d16', 'fpv5-d16', 'fp-armv8', 'arm1020t',
'arm1020e', 'arm1136jf-s', 'maverick', 'neon', 'neon-vfpv3',
'neon-fp16', 'neon-vfpv4', 'neon-fp-armv8', 'crypto-neon-fp-armv8',
'neon-fp-armv8.1' and 'crypto-neon-fp-armv8.1'.
In addition to determining which instructions are assembled, this
option also affects the way in which the '.double' assembler
directive behaves when assembling little-endian code.
The default is dependent on the processor selected. For
Architecture 5 or later, the default is to assemble for VFP
instructions; for earlier architectures the default is to assemble
for FPA instructions.
'-mthumb'
This option specifies that the assembler should start assembling
Thumb instructions; that is, it should behave as though the file
starts with a '.code 16' directive.
'-mthumb-interwork'
This option specifies that the output generated by the assembler
should be marked as supporting interworking. It also affects the
behaviour of the 'ADR' and 'ADRL' pseudo opcodes.
'-mimplicit-it=never'
'-mimplicit-it=always'
'-mimplicit-it=arm'
'-mimplicit-it=thumb'
The '-mimplicit-it' option controls the behavior of the assembler
when conditional instructions are not enclosed in IT blocks. There
are four possible behaviors. If 'never' is specified, such
constructs cause a warning in ARM code and an error in Thumb-2
code. If 'always' is specified, such constructs are accepted in
both ARM and Thumb-2 code, where the IT instruction is added
implicitly. If 'arm' is specified, such constructs are accepted in
ARM code and cause an error in Thumb-2 code. If 'thumb' is
specified, such constructs cause a warning in ARM code and are
accepted in Thumb-2 code. If you omit this option, the behavior is
equivalent to '-mimplicit-it=arm'.
'-mapcs-26'
'-mapcs-32'
These options specify that the output generated by the assembler
should be marked as supporting the indicated version of the Arm
Procedure. Calling Standard.
'-matpcs'
This option specifies that the output generated by the assembler
should be marked as supporting the Arm/Thumb Procedure Calling
Standard. If enabled this option will cause the assembler to
create an empty debugging section in the object file called
.arm.atpcs. Debuggers can use this to determine the ABI being used
by.
'-mapcs-float'
This indicates the floating point variant of the APCS should be
used. In this variant floating point arguments are passed in FP
registers rather than integer registers.
'-mapcs-reentrant'
This indicates that the reentrant variant of the APCS should be
used. This variant supports position independent code.
'-mfloat-abi=ABI'
This option specifies that the output generated by the assembler
should be marked as using specified floating point ABI. The
following values are recognized: 'soft', 'softfp' and 'hard'.
'-meabi=VER'
This option specifies which EABI version the produced object files
should conform to. The following values are recognized: 'gnu', '4'
and '5'.
'-EB'
This option specifies that the output generated by the assembler
should be marked as being encoded for a big-endian processor.
Note: If a program is being built for a system with big-endian data
and little-endian instructions then it should be assembled with the
'-EB' option, (all of it, code and data) and then linked with the
'--be8' option. This will reverse the endianness of the
instructions back to little-endian, but leave the data as
big-endian.
'-EL'
This option specifies that the output generated by the assembler
should be marked as being encoded for a little-endian processor.
'-k'
This option specifies that the output of the assembler should be
marked as position-independent code (PIC).
'--fix-v4bx'
Allow 'BX' instructions in ARMv4 code. This is intended for use
with the linker option of the same name.
'-mwarn-deprecated'
'-mno-warn-deprecated'
Enable or disable warnings about using deprecated options or
features. The default is to warn.
'-mccs'
Turns on CodeComposer Studio assembly syntax compatibility mode.
'-mwarn-syms'
'-mno-warn-syms'
Enable or disable warnings about symbols that match the names of
ARM instructions. The default is to warn.
Info Catalog
as: ARM-Dependent
as: ARM Syntax